哇酷®开发者社区(WhyCan® Forum)

达克罗德 wrote:

Gardenia wrote:

楼主休完假了吧？我这边也是需要图形的，方便发我邮箱吗？4201842@qq.com

我试了一下发现我的改动太分散，而且xboot和我另外一个框架绑在一起，不好给你，我还是给你说下几个改动吧

1. skip compress [sys-copyself.c]

+#if CONFIG_LZ_COMPRESS
sys_spi_flash_init();
sys_spi_flash_read(16384, &z, sizeof(struct zdesc_t));
sys_spi_flash_exit();
...
sys_decompress(tmp, ssize, mem, dsize);
}
else
+#endif

1. Disable logs [arch/arm32/mach-f1c100s/include/configs.h]

+#define CONFIG_NO_LOG (1)

1. 优化了SPI读写
   ```
   /*

• sys-spi-flash.c
  *

• Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>

• Official site: http://xboot.org

• Mobile phone: +86-18665388956

• QQ: 8192542
  *

• This program is free software; you can redistribute it and/or modify

• it under the terms of the GNU General Public License as published by

• the Free Software Foundation; either version 2 of the License, or

• (at your option) any later version.
  *

• This program is distributed in the hope that it will be useful,

• but WITHOUT ANY WARRANTY; without even the implied warranty of

• MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

• GNU General Public License for more details.
  *

• You should have received a copy of the GNU General Public License

• along with this program; if not, write to the Free Software Foundation,

• Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  *
  */

#include <xboot.h>

enum {
SPI_GCR = 0x04,
SPI_TCR = 0x08,
SPI_IER = 0x10,
SPI_ISR = 0x14,
SPI_FCR = 0x18,
SPI_FSR = 0x1c,
SPI_WCR = 0x20,
SPI_CCR = 0x24,
SPI_MBC = 0x30,
SPI_MTC = 0x34,
SPI_BCC = 0x38,
SPI_TXD = 0x200,
SPI_RXD = 0x300,
};

void sys_spi_flash_init(void)
{
virtual_addr_t addr;
u32_t val;

/ Config GPIOC0, GPIOC1, GPIOC2 and GPIOC3 /
addr = 0x01c20848 + 0x00;
val = read32(addr);
val &= ~(0xf << ((0 & 0x7) << 2));
val |= ((0x2 & 0x7) << ((0 & 0x7) << 2));
write32(addr, val);

val = read32(addr);
val &= ~(0xf << ((1 & 0x7) << 2));
val |= ((0x2 & 0x7) << ((1 & 0x7) << 2));
write32(addr, val);

val = read32(addr);
val &= ~(0xf << ((2 & 0x7) << 2));
val |= ((0x2 & 0x7) << ((2 & 0x7) << 2));
write32(addr, val);

val = read32(addr);
val &= ~(0xf << ((3 & 0x7) << 2));
val |= ((0x2 & 0x7) << ((3 & 0x7) << 2));
write32(addr, val);

/ Deassert spi0 reset /
addr = 0x01c202c0;
val = read32(addr);
val |= (1 << 20);
write32(addr, val);

/ Open the spi0 bus gate /
addr = 0x01c20000 + 0x60;
val = read32(addr);
val |= (1 << 20);
write32(addr, val);

/ Set spi clock rate control register, divided by 4 /
addr = 0x01c05000;
write32(addr + SPI_CCR, 0x00001000);

/ Enable spi0 and do a soft reset /
addr = 0x01c05000;
val = read32(addr + SPI_GCR);
val |= (1 << 31) | (1 << 7) | (1 << 1) | (1 << 0);
write32(addr + SPI_GCR, val);
while(read32(addr + SPI_GCR) & (1 << 31));

val = read32(addr + SPI_TCR);
val &= ~(0x3 << 0);
val |= (1 << 6) | (1 << 2);
write32(addr + SPI_TCR, val);

val = read32(addr + SPI_FCR);
val |= (1 << 31) | (1 << 15);
write32(addr + SPI_FCR, val);
}

void sys_spi_flash_exit(void)
{
virtual_addr_t addr = 0x01c05000;
u32_t val;

/ Disable the spi0 controller /
val = read32(addr + SPI_GCR);
val &= ~((1 << 1) | (1 << 0));
write32(addr + SPI_GCR, val);
}

static void sys_spi_select(void)
{
virtual_addr_t addr = 0x01c05000;
u32_t val;

val = read32(addr + SPI_TCR);
val &= ~((0x3 << 4) | (0x1 << 7));
val |= ((0 & 0x3) << 4) | (0x0 << 7);
write32(addr + SPI_TCR, val);
}

static void sys_spi_deselect(void)
{
virtual_addr_t addr = 0x01c05000;
u32_t val;

val = read32(addr + SPI_TCR);
val &= ~((0x3 << 4) | (0x1 << 7));
val |= ((0 & 0x3) << 4) | (0x1 << 7);
write32(addr + SPI_TCR, val);
}
#define SPI0_BASE (0x01c05000)
static inline void sys_spi_write_txbuf(u8_t * buf, int len)
{
// virtual_addr_t addr = 0x01c05000;
int i;

if(!buf)
len = 0;

write32(SPI0_BASE + SPI_MTC, len & 0xffffff);
write32(SPI0_BASE + SPI_BCC, len & 0xffffff);
for(i = 0; i < len; ++i)
write8(SPI0_BASE + SPI_TXD, *buf++);
}

static int sys_spi_transfer(void txbuf, void rxbuf, int len)
{
// virtual_addr_t addr = 0x01c05000;
int count = len;
u8_t * tx = txbuf;
u8_t * rx = rxbuf;
u8_t val;
int n, i;

while(count > 0)
{
n = (count <= 64) ? count : 64;
write32(SPI0_BASE + SPI_MBC, n);
sys_spi_write_txbuf(tx, n);
write32(SPI0_BASE + SPI_TCR, read32(SPI0_BASE + SPI_TCR) | (1 << 31));

// while((read32(SPI0_BASE + SPI_FSR) & 0xff) < n);
for(i = 0; i < n; i++)
{
while((read32(SPI0_BASE + SPI_FSR) & 0xff) == 0);
val = read8(SPI0_BASE + SPI_RXD);
if(rx)
*rx++ = val;
}

if(tx)
tx += n;
count -= n;
}
return len;
}

static int sys_spi_write_then_read(void txbuf, int txlen, void rxbuf, int rxlen)
{
if(sys_spi_transfer(txbuf, NULL, txlen) != txlen)
return -1;
if(sys_spi_transfer(NULL, rxbuf, rxlen) != rxlen)
return -1;
return 0;
}

void sys_spi_flash_read(int addr, void * buf, int count)
{
u8_t tx[4];

tx[0] = 0x03;
tx[1] = (u8_t)(addr >> 16);
tx[2] = (u8_t)(addr >> 8);
tx[3] = (u8_t)(addr >> 0);
sys_spi_select();
sys_spi_write_then_read(tx, 4, buf, count);
sys_spi_deselect();
}

4. Remove shells and Lua frameworks

> +#if XBOOT_SHELL_ENABLE
>      /* Do auto boot */
> Add a comment to this line
>      do_autoboot();
>          //run_shell();
>                  system("/application/examples");
>      }
> +#else
> +    while(1);
> +#endif
>
> make file remove these lines:
> -                framework                                    \
> -                framework/base64                            \
> -                framework/display                            \
> -                framework/event                                \
> -                framework/hardware                            \
> -                framework/lang                                \
> -                framework/stopwatch                            \
>
> -INCDIRS        +=     xboot/src/external/lua-5.3.4
> -SRCDIRS        +=    xboot/src/external/lua-5.3.4
> -INCDIRS        +=     xboot/src/external/lua-cjson-2.1.0
> -SRCDIRS        +=    xboot/src/external/lua-cjson-2.1.0
>
> 再把romdisk删掉一些，我只留了ttf文件

5. 参照xboot最新版，加上编译选项 —ffunction-sections和—gc-sections [这个一定要做，能省1.xMB]

6. SPI升到100MHz [arch/arm32/mach-f1c100s/sys-spi-flash.c]
-    write32(addr + SPI_CCR, 0x00001001);
+    write32(addr + SPI_CCR, 0x00001000);

7. CPU生到最高频率720Mhz [arch/arm32/mach-f1c100s/sys-clock.c]
-    clock_set_pll_cpu(408000000);
+    clock_set_pll_cpu(800000000);

达克罗德 wrote:

Gardenia wrote:

达克罗德 wrote:

framebuffer驱动我还是花了几个晚上功夫的，为了不用xboot的dts还有driver架构，把reset，clock等好几个模块都改了一遍。如果再来一遍V3S的话，应该容易很多，因为两芯片同出一源代码很类似。

不过不打算继续自己搞裸奔了，可重用性太低，累死人。准备直接用xboot或者RTOS这样的平台来开发后续产品，开发驱动有标准，代码容易复用，功能也更强大。比如说切换V3S和F1C100S对xboot来说非常简单，上层完全不用改

目前我把xboot优化到1.3MB大小（带文件系统和图形库），启动到logo只需要0.85s（F1C100S），基本满足需要。V3S没测，上电应该更快。如果V3S和F1C100S支持QSPI就完美了。。。

:lol:现在才看到，原来你已搞定，能分享下代码吗？我信息里面有我邮箱
我也想试试能不能启动之后能不能先初始化spi，提高下spi访问速度，之后spi拷贝速度会高点，没有qspi确实硬伤啊

在老家，只能回去之后整理给你。
我试过把spi速度提高到100mhz，还有优化底层读fifo的代码，提升非常有限
800ms其中有400ms是全志内部boot代码读spl和启动的时间，这时候spi速度只有3mhz，这还没法改，没办法这是全志写死了。所以优化空间也不多了

路人甲 wrote:

Gardenia wrote:

达克罗德 wrote:

framebuffer驱动我还是花了几个晚上功夫的，为了不用xboot的dts还有driver架构，把reset，clock等好几个模块都改了一遍。如果再来一遍V3S的话，应该容易很多，因为两芯片同出一源代码很类似。

不过不打算继续自己搞裸奔了，可重用性太低，累死人。准备直接用xboot或者RTOS这样的平台来开发后续产品，开发驱动有标准，代码容易复用，功能也更强大。比如说切换V3S和F1C100S对xboot来说非常简单，上层完全不用改

目前我把xboot优化到1.3MB大小（带文件系统和图形库），启动到logo只需要0.85s（F1C100S），基本满足需要。V3S没测，上电应该更快。如果V3S和F1C100S支持QSPI就完美了。。。

:lol:现在才看到，原来你已搞定，能分享下代码吗？我信息里面有我邮箱
我也想试试能不能启动之后能不能先初始化spi，提高下spi访问速度，之后spi拷贝速度会高点，没有qspi确实硬伤啊

没有quad spi,但是貌似有dual spi吧。

晕哥 wrote:

Gardenia wrote:

晕哥 wrote:

移植一个 libpng 就支持 png图片了。

xboot本身就集成了 libpng.

嗯，看到了，xboot启动时间比较慢，如果要做到1秒以内启动，晕哥有没试过？有可行性不？

主要耗时在于spl(boot0)从spi 拷贝 xboot(boot1) 到DRAM,
想办法精简 xboot, 或者分时加载 xboot, 比如再弄个boot2, 系统boot1启动后再加载boot2.